The collaboration centers on implementing PQSecure’s CRYSTAL-1000C IP core—which targets NIST’s FIPS 203 and FIPS 204 standards—directly into QuickLogic’s eFPGA Hard IP fabric. During testing on the Intel 18A process node, the cryptographic engine proved capable of integration within existing ASIC designs while retaining enough capacity to support additional security measures, such as side-channel masking.

This architecture addresses the inherent rigidity of fixed-silicon chips. By utilizing QuickLogic’s Aurora programming tools, designers can adjust their eFPGA configuration to balance power efficiency against high-performance requirements. For the end user, this means the ability to load new bitstreams to patch vulnerabilities or shift between hybrid classical and quantum modes as global standards evolve. According to Trey Peterson, a field applications engineer at QuickLogic, the partnership provides a necessary buffer for designers who otherwise risk being locked into outdated hardware as the threat landscape shifts.