The new G1 IP leverages SONOS technology to provide a 256KB program flash macro alongside a 1KB data flash component. Crucially, the design adds this functionality to TSMC’s platform without requiring modifications to the original process design kit. This allows automotive chipmakers to integrate the memory solution while maintaining existing design workflows and qualified manufacturing parameters.

Floadia confirmed the IP has passed AEC-Q100 Grade 1 qualification, validating its durability for harsh automotive environments. Engineering teams can now utilize the 1KB data flash for EEPROM-style storage, featuring 100,000 program/erase cycles. System efficiency is further bolstered by an internal charge pump that removes the need for external high-voltage hardware, while integrated ECC interfaces provide parity-bit error correction to safeguard data integrity over the vehicle's lifespan. With erase times clocked under 20ms, the architecture is specifically tuned for the rapid firmware updates required by modern body electronics and powertrain controllers.