The company’s new X-SRAM technology targets the on-chip memory gap, offering up to 5× higher density than conventional SRAM while remaining compatible with standard nanosheet logic processes. By overcoming the scaling slowdowns inherent in traditional CMOS processes, this architecture aims to provide the high-speed cache performance required by modern GPUs and AI processors.

Complementing the on-chip improvements, 3D X-DRAM utilizes manufacturing techniques derived from 3D NAND to push HBM capacity up to 10× beyond current 2D DRAM limits. CEO Andy Hsu, who will present the platform at the FMS 2026 conference, describes these developments as a fundamental shift in how AI hardware manages data flow. Stan Shih, a former TSMC board director and current advisor to the firm, noted that these innovations provide a necessary technical pathway for the global semiconductor industry to sustain the rapid growth of AI infrastructure.